The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a semiconductor fin having a wide semiconductor fin base that is isolated from a device channel by a dielectric layer and a method of forming the same. The wide semiconductor fin base improves source/drain epitaxy for better doping incorporation and strain enhancement.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. Bulk FinFETs face scaling challenges due to inferior short-channel control compared with semiconductor-on-insulator (SOI) FinFETs. However, FinFETs formed on SOI substrates are more costly than FinFETs formed on a bulk semiconductor substrate and SOI fabrication requires special foundry support not needed with bulk semiconductor substrates.
Dielectric isolated FinFETs (i.e., forming SOI channel FinFETs) reconciles the concerns on bulk and SOI FinFETs. However, to maximize the channel strain by embedded source/drain (eS/D) epitaxy, the conventional eS/D epitaxy quality is compromised due to the narrow feed seed layer for epitaxial growth. Therefore, there is a need for improving FinFETs with dielectric isolation.